Demand for AI chips is growing exponentially, but costs and complexity limit the technology to a handful of companies.
The explosive demand for AI chips is pushing semiconductor manufacturing to its limits, with extreme ultraviolet (EUV) lithography emerging as the key enabler for advanced-node production. However, the cost and complexity of EUV remain major barriers, limiting its adoption to a handful of companies: TSMC, Samsung, Intel, SK Hynix, Micron, and the emerging Rapidus (Japan). Rapidus is still ramping up and plans to begin high-volume EUV production in 2027. While high-NA EUV promises to push fabrication below 2nm, ASML’s production bottlenecks, resist material challenges, and mask infrastructure constraints continue to slow adoption. To bridge the gap, AI-driven process control, novel resist chemistries, and government-backed research initiatives are accelerating EUV’s efficiency. The semiconductor industry faces a defining challenge—can EUV scale fast enough to meet the insatiable demand for AI hardware, or will alternative lithography techniques keep pace?
My Take
Scaling EUV isn’t just about better tools—it’s about expanding access beyond the few players who control it today. The biggest challenge isn’t just cost—it’s ASML’s production bottleneck and the lack of a second EUV supplier. Even if ASML ramps up, EUV remains too expensive and energy-intensive for most fabs. A multi-pronged approach is needed—governments funding shared EUV hubs, fabs reducing reliance on full EUV adoption by integrating hybrid lithography, and breakthroughs in resist materials and power-efficient EUV sources—to prevent AI innovation from being throttled by EUV supply constraints.
By using EUV only for the most critical layers while relying on DUV lithography with multi-patterning for others, fabs can lower costs and extend the life of existing equipment without sacrificing technological progress. The EUV Accelerator in Albany, New York, and imec in Belgium are examples of shared EUV hubs, providing multiple companies and researchers with open access to EUV tools, accelerating process development, and easing barriers to advanced-node adoption.
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Credit: Semiconductor Engineering
This post reflects my own thoughts and analysis, whether informed by media reports, personal insights, or professional experience. While enhanced with AI assistance, it has been thoroughly reviewed and edited to ensure clarity and relevance.